Introduction to Asynchronous Sample Rate Converters (ASRC) for Jitter Reduction*
Jitter on the clock that drives the DAC will increase noise and distortion. The effect is more significant as the incoming audio signal to the DAC increases in frequency.
An Asynchronous Sample Rate Converter (ASRC) is built into all ESS DACs. Looking at the chart in Part I, it can be seen that separate ASRC ICs, placed before the DAC, were deployed in a few products. ASRCs may also be imbedded in the DSP chips in which case it is impossible to identify from the schematics. Since the ASRC is directly before the DAC, it will attenuate jitter of digital sources such as SPDIF, HDMI and asynchronous USB2 (older USB transceivers may generate too much jitter to be fully attenuated). If the source is encoded in lossless or lossy form it must be transcoded to linear PCM. ASRCs designs, which have been published, cannot attenuate jitter directly on a DSD (SACD) encoded signal and DSD must also be transcoded to Linear Pulse Code Modulation (LPCM) first.
ESS claims its ASRC can work directly on the DSD stream, at the DSD data rate, and will reject jitter on DSD data. I have no information on how ESS does this. Below I consider only the use of an ASRC for LPCM data.
The ASRC processes the incoming LPCM data, and the LPCM data that leaves the chip is not the same as what came in. To understand this, let us look at a conceptual ASRC. An ideal DAC is clocked with one oscillator. The DAC, after reconstruction filtering, drives an ideal ADC clocked by a different oscillator. This conceptual ASRC is illustrated as a block diagram in below.
Note that the ASRC does not produce a clock. It just provides a mechanism to interface the LPCM signal between to clocks that already exist. Clearly, the LPCM data entering the ideal DAC are not the same as what is exiting the ideal ADC if the clocks are different frequencies.
The ASRC can take in a clock with jitter on the LPCM input side and produce a jitter-free clock on the LPCM output side. Does this not imply all the jitter has been rejected? No! The effects of the jitter (increased SNR and distortion above what is measured with jitter-free clocks) may be present on the LPCM data exiting the ASRC. The worst-case situation is the mixed-signal example shown above. The DAC rejects none of the jitter on the clock driving it. All the distortion and noise resulting from the jitter is now part of the LPCM data leaving the ADC.
ASRCs, in practice, are fully digital and have no internal DAC or ADCs. A fully digital ASRC interpolates (up-samples) the LPCM input data to a very high sampling rate, which is then re-sampled at the output clock’s rate. The system just described is impractical to integrate. Digital designers have developed systems that can emulate the functionality in less silicon.
Artefacts from the design limitations for a practical all-digital ASRC are small frequency response variations and distortion components in the LPCM data at the output. These arise in the process of the sample-rate conversion (no jitter on the clocks).
A practical fully-digital chip ASRC will reject some jitter. A section of the digital circuitry estimates the frequency ratio of the two clocks. The rate at which this estimate can change is limited. Robert Adams, who created the first ASRC for an audio application, points out the estimate is “computed using thousands of past input and output sample clock events and is therefore immune to small perturbations in the arrival time of any clock edge.”
The ratio estimate becomes less effective the faster the clock edge arrival time changes. Some ASRC data sheets offer a graph that demonstrates how fast the clock edge arrival times must vary for the ratio estimator to become insensitive to it. While this graph is useful for the designer of the Pre/Pro, it cannot replace graphs showing SNR and distortion increase with different types of jitter present on one of the clocks.
*See Note following Conclusions
Introduction to Digital Filtering of an LPCM Signal and DAC Digital Filter Performance*
Artefacts from the sampling process, called folded tones, are removed during the process of increasing the sampling rate.
For a band-limited 20kHz analog signal sampled at a rate of 44.1kHz samples/sec (fs), the spectra appear around 0Hz (desired signal) as well as from 24.1kHz to 64.1kHz and then repeat around multiples of 44.1kHz. The repeating spectra are the stop-band images from the sampling process. For a 20kHz signal (fB), the right side of the first image (often called the folded frequency) is close-in at 22.1kHz (44.1kHz – 20kHz). The suppression of the stop-band images allows the sampled signal to better represent an analog signal sampled at 44.1kHz. Information lost from band limiting of the signal before the sampling process during recording cannot be restored, although some manufactures try to imply this. For high resolution files, fs will be between 88.2 – 192kHz. The maximum frequency that can be recorded (fB) can also be extended since the right side of the first image will be at a higher frequency.
The process of attenuating the stop-band images of a sampled signal takes place in the digital filters on the DAC, although these can be bypassed and replaced by external digital filters. To my knowledge, the only multichannel products to do this are from Cambridge Audio.
In general, DAC ICs with better SNR and THD specs devote more silicon to the filtering function. If the digital filter does not have a sufficiently low stopband rejection past half the sampling rate, the folded tones from the reconstruction process may dominate the harmonic distortion and noise spectra of the DAC when driven with a sine wave test tones. As the input frequency increases, the first folded tone frequencies move in the opposite direction. The performance of the digital filter is most significant under these conditions since the folded tones are moving towards half the sampling rate (22.1kHz for a CD). It is also possible for the folded tones to intermodulate with the harmonic distortion components giving rise to tones in the pass band.
The stopband rejection of the digital filter is increased by increasing the complexity of the filter. This involves increasing the order (number of zeros) to the filter. This increases the amount of silicon that must be devoted to the filter which increases the price of the DAC IC.
For the DACs at the top of an IC vendors line, with worst case THD, at full scale, ranging for -100dB to -110dB, the stopband attenuation will typically range from -100dB – 120dB below the unity gain. The stopband performance is specified in the datasheets found on the web for all but the ESS products.
It thus should come as no surprise that the parts with a lower performing analog section were the first to be made available as octal DACs. These parts also minimize the amount of silicon taken by the digital filter. This can be seen in a stopband rejection in the range of -55dB to -60dB.
For high resolution material, the folded tones are more widely spaced from the highest frequency of the desired signal. All DACs will achieve very high attenuation of folded tones for this reason.
A few data sheets for data converters and ASRCs, notably the ESS products, the number of bits in the data path or multiply-accumulate section of the digital signal processor are presented. The large number of extra bits, relative to the analog resolution of the DAC in effective bits, is required to prevent round off error in the computations. Digital filter coefficients must also be specified with extreme accuracy. While these numbers may be useful to estimate the passband and stopband characteristics of the digital filter, and it is far more useful, from the designer’s standpoint, to look at the actual pass band and stop band characteristics of the digital filters. This is not supplied on the ESS public data sheets.
The passband frequency response also changes as the digital filter gets more complex. For the simplest filter found on the lowest priced DAC, the variation may be +/-0.1dB. For the very complex filter on the TI PCM 1972, the deviation is +/- 0.00001 dB. Mid-priced parts may be a couple orders less than this, but the digital filter passband frequency response is clearly dominated by the analog electronics.
*See Note following Conclusions
Building a Pre/Pro with Pre-Designed Boards
Often the company designing a Pre/Pro may not have the staff to implement all diverse functions found in this product category. Vendors often use pre-designed PC boards to speed the design process, but the cost is higher than if the design is done internally. It is likely that the analog functions highlighted in this article will be taken on by the company that sells the product. Third- party PC boards that perform the DSP and HDMI functions are often found in Pre/Pros with limited production runs. The cost of designing these boards in-house far exceeds what could be recovered at these low production volumes.
Kuusama Audio specializes in PC boards for Pre/Pros with Cirrus DSPs at the center:
Momentum Data System specializes in providing PC boards for Pre/Pros with TI DSPs at the center. The last page of this document shows how the company’s PC is interconnected:
The Momentum Data Systems (MDS) DSP board cited in the document (DAE 77) includes an ASRC between the two DSPs. This, or similar, Momentum Data Systems boards can be identified in several premium-priced Pre/Pros. Some Momentum Data Systems boards have lower cost DACs on the board to simplify a prototype design. I have been surprised to see MDS boards with these DACs included on some very expensive Pre/Pros. MDS sells production boards with the data converters removed. Regardless of the design quality of the analog electronics and the parts quality, the DAC performance will dominate the terminal characteristics.
A More Detailed View of the Internal Signal Flow in the Large Scale Integrated Circuit (LSI) Analog AVR chip
Below is a block diagram of the chip when connected to the DAC which, in turn, is connected to the preamp outputs. The DAC and reconstruction filter are external to the LSI chip at the left of the drawing. The switch in the LSI chip is positioned to allow the DAC output to appear at the volume control input.
As noted on the diagram, the volume control represents a low impedance load established by the resistor string. Current must flow through the switch to drive the volume control input.
Current flowing through a transistor switch causes distortion. The complex phenomenon is well explained by Douglas Self in his “Small Signal Audio Design” text. Chapter 16 covers the complete topic of switch design for audio circuits. I also mention this text as a solid reference in the op-amp section above.
For this simplified diagram, the transistor switches and the tapped resistor for the electronic volume control are not shown. These components are assumed to be inside the round block.
Transistors switches used to select the appropriate tap on the resistor string of the electronic volume control have no current flowing in them. The other end of the electronic volume control switches are connected to the IC buffer following the volume control.
The input impedance of the buffer is very high, and no current flows from the switches inside the volume control to the input of buffer; consequently, there is no voltage drop across the switches inside the volume control.
The output impedance of the buffer is low, and it has no problem driving the preamp outputs or power amp inputs.
Pre/Pros implemented with Small Scale Integrated (SSI) chips have an additional op-amp buffer placed between the switch (on its own chip) and the volume control (on its own chip). With the added buffer in place, there is no current flowing in the switch connected to the volume control; consequently, the switch has no voltage drop across it. This is described in more detail below.
Some Rohm versions of the analog LSI AVR chip have this additional buffer, adding eight more op-amps to the chip. The Rohm chip’s data sheet suggests the chip has half the distortion of the top of the line New Japan Radio (JRC) LSI AVR chip, which has no added buffer
Like all active electronic devices, a buffer adds noise to the signal that passes through it. In an SSI implementation, very low noise standalone op-amps would be used for both buffers. The small opamps in the LSI AVR chips produce more noise. This can be seen in the data sheets with the New Japan Radio (JRC) chip emitting less output noise than the Rohm chip. Herein is the engineering tradeoff between noise and distortion performance resulting from the performance limitations of the op-amps inside the LSI chip.
The Pioneer SC-79 uses the Rohm BD3473KS2 LSI AVR, which has been reviewed in Secrets.
For this sample, measured SNR was 17.8 bits, equivalent flat 20Hz – 20KHz referenced to 2VRMS at unity gain. This is an admirable result. Distortion was less impressive. No product with a JRC chip has been bench tested with the Audio Precision at Secrets.
The block diagram of the LSI chip when the 7.1 input is selected is shown below.
This diagram illustrates the signal flow when the switch position allows voltage at the 7.1 input to transfer to the switch. The signal path for the DAC and 7.1 direct mode are the same; only the switch position is changed. The amounts of noise and distortion introduced by the switch, volume control, and output buffer are the same for the 7.1 channel analog input signal, in direct mode, as when the DAC is applied to the LSI chip (previous block diagram).
The next figure is a block diagram of the LSI chip when a pair of stereo inputs is selected.
Analog stereo signals are further degraded since they must pass through another small switch that is part of the input selector. When switches are connected in series, the voltage drop across the pair is larger and the distortion more pronounced.
Some JRC chips place a pair of buffers after the two-channel selector switch to prevent this problem, but the buffers introduce a high DC offset that must be removed by external blocking capacitors. Added external components increase cost as well as and take PC board space, and as a result, some designers may use a different part in response to this. The JRC NJW1299 AVR LSI used in some Denon products does not have the added buffers.
Use of the LSI AVR chip in Stereo Applications
The LSI AVR chip provides so many functions at a low cost, that aspects of its functionality can be deployed in other product categories. The $500 Yamaha R-S700 stereo receiver reviewed on this site uses the Renesas chip but uses it in a balanced mode to significantly reduce the chips distortion and the dynamic range doubled.
For the CD input, the electronic volume section runs in the balanced mode with four of the eight volume controls on the chip in conjunction with external op-amps. The input selector is bypassed, and the balanced signals connect to four of the eight direct inputs. The comprehensive support for tape recorders in the R-S700, rare for a stereo product in this price category, is made possible by two independent stereo input selectors of the Renesas chip.
Conclusions about LSI AVR Block Diagrams
Performance limitations arise from interconnections of subcomponents in the LSI AVR chip. Alongside the performance deficit of each subcomponent, compared with its SSI counterparts, distortion of the chip is significantly higher.
A block diagram of the LSI AVR chip with the signal routing from the selector switch to the two-channel ADC is not presented. The ADC path is operative when the DSP signal processor functions are enabled, as opposed to the direct-mode stereo path. I will present the block diagram in a potential companion piece that comments on the quality of ADCs in AVRs and Pre/Pros.
Low Distortion Switching with SSI CMOS Switch Blocks and Separate Op-Amps
In an SSI implementation, a unit gain op-amp buffer always follows the two-channel selector switch to prevent any current flow in the switch. This prevents any distortion from occurring at the switch as a result of current flow through the CMOS switch.
Often, in an SSI implementation, an additional extra op-amp stage, wired as a buffer, is connected to each of the RCA input jacks. The buffer’s output is connected to SSI selector switch and provides a low impedance path to the selector switch’s input. The low impedance reduces the switch distortion that occurs even when no current flows in the switch. Without the buffer, the component connected to the RCA jack, which has an unknown, likely higher, output impedance, would drive the switch directly.
The total number of op-amps for input buffering function (one per stereo input jack) far exceeds the number that could be integrated on the AVR LSI chip.
Replacing the solid state switches with relays in an SSI implementation eliminates all the electronics associated with the two-channel input selection subsection. Pre/Pros have so many switching functions it is cost prohibitive to replace them all with relays, in contrast with a two-channel preamp that often uses relays exclusively. The only Pre/Pro schematic I have seen using exclusively relays is the Bryston SSP-3. The SSP-3 has 34 relays (stereo pair in each) including relays for anti-thump protection at the output.
The complex diagram below shows an SSI implementation of a Pre/Pro. This could also represent the block diagram of a stereo preamp ignoring the 7.1 input.
The overall performance of a Pre/Pro, stereo preamp, or DAC box, is limited by the weakest performing parts in the signal chain. In this article series, I have reviewed the key sections of the signal chain and introduced options that can improve the performance of each stage. Specific ICs were discussed. Some parts, which provide improved performance, have been recently introduced. Part numbers for DACs, op-amps, digital volume controls and ASRCs used can be found on the website or printed literature from some enlightened companies
Those considering the purchase of an expensive component, with a technical background, might consider the purchase of a service manual to see the detailed part selection shown in the schematics. Unfortunately only a few large companies will provide these to consumers at a reasonable price. When I gain access to this material on a piece of equipment under review, I will try to produce a sidebar that highlights the internal construction.
The large number (8-12) of channels of a Pre/Pro makes it impractical to design a unit using the best analog ICs and mono DACs. The price would be so prohibitive that even designers of very high-end home theaters would find it excessive. Another limiting factor on the circuit design for the audio section is the high cost of supporting video functions. For these functions, the dominant cost may be related to development of firmware and license fees.
Often, third parties are contracted for engineering support and design of complete PC boards of subassemblies. The ever changing requirements on the video side gives the product a short shelf life, requiring the development fees to be spread over the smaller number of units produced. Customer support levels become high as a result of HDMI interface issues with other products connected to the unit.
In contrast, stereo units can be produced at a reasonable cost while still use the best performing sub-blocks and can take advantage of advanced circuit techniques, such as balanced volume controls. With the advent of high resolution stereo music files, we are seeing a bifurcation between the build quality of affordable stereo and the most expensive multi-channel equipment.
These issues played out at CEDIA 2013 with few new multi-channel Pre/Pro products exhibited by smaller companies. Instead, dual-domain stereo products for high-resolution audio were introduced in large numbers by companies that have invested the past decade producing high-end Pre/Pros.
The presence of LSI AVR chip in ever higher priced multi-channel products from the Far East points to the need to have multi-channel and stereo units on the same equipment rack.
- Measurements of new products being reviewed at Secrets were used to support the work presented in this article. Each of these products uses a different volume control and two use ESS DACs.
- Chris Heinonen produced the measurements using the Audio Precision APx585 analyser. Units tested included the Pioneer SC-79 AVR which employs the Rohm BD3473KS2 LSI AVR. Additional units included the Marantz AV7705 and Yamaha CX-A 5000 Pre/Pros both using the Renesas R2A15220FP LSI AVR.
- Also tested by Chris Heinonen, was the Arcam AVR750 that uses the SSI implementation with a Cirrus CS3318 digital volume control chip.
- Audio Precision data for stereo preamps used for this article are currently on the website. The products were the Classe CP-800 and Emotiva XSP-1 Stereo Preamplifiers. The units use the TI PGA3310 and MUSES 72320 digital volume controls respectively. Both units used the balanced volume control configuration. These measurements were by Dr. John E. Johnson, Jr.
*These sections appeared in slightly modified form in my review:
I would like to thank Jay Haider for reviewing this article.
* The first two sections (Introduction to Asynchronous Sample Rate Converters (ASRC) for Jitter Reduction and Introduction to Digital Filtering of an LPCM Signal and DAC digital filter performance) are modified from Part 2 of the HK 990 review. The material in these first two sections has been enhanced to cover a number of DACs and ASRCs and not just the parts used in the HK 990.