Technical Articles and Editorials
- Written by Dr. David A. Rich
- Published on 23 September 2013
- AVR - Audio Video Receiver - Build Quality: Part I
- Page 2: Understanding DAC Specifications
- Page 3: Digital Reconstruction Filter
- Page 4: Number of DACs per Chip
- Page 5: Improved Distortion and Noise Performance with Balanced DAC Output
- Page 6: Enhanced Distortion Performance with Current Mode DACs
- Page 7: Multiple DACs Combined to Produce a Single Channel
- Page 8: Chart Presenting Build DACs used in AVRs Across Manufacturers and Price
- Page 9: The Right Side of the Chart: More Details about the AVRs and Pre/Pros
- Page 10: The concept of Effective Bits
- Page 11: Single Chip Analog AVR LSI
- Page 12: Enhanced Performance with SSI Parts
- Page 13: Limitations of Operational Amplifier Performance with the Single Chip Analog AVR LSI
- Page 14: Limitations on the Performance of Semiconductor Switches with the Single-Chip Analog AVR LSI
- Page 15: Use of Relays to Achieve Better Performance
- Page 16: A Very Brief Look at Changes in Power Amps in AVRs
- Page 17: Conclusions
- All Pages
Understanding DAC Specifications
The most important aspect of DAC performance is SNR, followed by level linearity error, pattern noise and THD. Other factors to note are whether the DAC is balanced or unbalanced, whether the DAC is a current-source device or a voltage-source device and the number of DAC channels inside the package"
The price of a DAC IC increases with performance. Improved performance is typically related to the size of the silicon utilized by the chip. Over time, performance improves for a constant price, especially for the entry level DACs. This is a consequence of innovations in circuit design and process technology.
A DAC manufacturer's worst-case specification on a datasheet establishes a performance bound (the lowest performance acceptable). If the DAC chip does not exceed the tests specification with the bound, then it is thrown out. Most chips that pass have better than worst-case performance. AVR designers must work with the worst-case numbers for all integrated circuits (ICs) to determine the unit's overall worst-case performance. The final worst case terminal specifications of the AVR provided to the consumer are set by the summation of the worst case specifications of the individual IC in cascade inside the unit. Unfortunately, most datasheets for analog ICs present worst-case values for only a few specifications. Most specifications provide only "typical" values. The percentage of parts that achieve this typical value is not specified.
Signal to Noise Ratio (SNR) dominates the DAC's performance across the majority of the signal levels. Only as the signal level approaches 1/20 of the full-scale signal level does Total Harmonic Distortion (THD) assert itself.
Most DAC suppliers only provide SNR measurements with an A-weighted filter in the signal path. The A-weighted filter rolls off the low end of the spectrum, which is said to correspond to hearing test curves that show the ear is less sensitive to low frequency noise. The sensitivity of the ears to low frequency tones changes with SPL, so A-weighting often underestimates the perceived noise level.
Since the noise of a transistor, especially a MOSFET, tends to rise at low frequencies, adding the filter improves SNR when compared with an unfiltered measurement more than if the noise source were flat for all frequencies.
The deviation in amplitude of a sine wave from the theoretical value, as the digital input signal level is reduced, is also important. This is often called level linearity error. Level linearity error should also be checked at different frequencies and sampling rates, but one is lucky to find a single specification on most data sheets.
The noise floor of some DACs may have audible tones that cannot be observed using standard tests for DACs. These quasi-periodic oscillations are called pattern noise, idle-channel tones, or modulation noise. Quasi-periodic signals are difficult to measure; rarely, will it show itself as a distinct line in a spectral plot. Nonetheless, our ears can detect the tonality. These quasi-periodic tones can be observed by changing the digital equivalent of a DC voltage as it is applied to the DAC and monitoring the SNR. Other test methodologies have been proposed to produce a measurable result when the converter is exhibiting this behavior. The following reference offers additional information and includes extensive references:
The paper below by ESS engineers looks like an IEEE paper, but in fact it was never reviewed or published. Section IV of the paper addresses how ESS attempts to remove the quasi-periodic coloration of the noise floor.
Full scale THD at 1 kHz does not fully characterize the performance of the DAC. Distortion performance varies with the full frequency range from 20 Hz to 20 kHz. THD tends to increase with increasing frequency.