AVR – Audio Video Receiver – Build Quality: Part III – Component Choices for a High Performance Design
- Written by David A. Rich
- Published on 03 March 2014
- AVR – Audio Video Receiver – Build Quality: Part III – Component Choices for a High Performance Design
- Page 2: Introduction to Digital Filtering of an LPCM Signal and DAC digital filter performance*
- Page 3: Building a Pre/Pro with pre-designed boards
- Page 4: A More detailed view of the internal signal flow in the Large Scale Integrated Circuit (LSI) analog AVR chip
- Page 5: Use of the LSI AVR chip in Stereo Applications
- Page 6: Conclusions about LSI AVR block diagrams
- Page 7: Low distortion switching with SSI CMOS switch blocks and separate op-amps
- Page 8: Final Analysis
- All Pages
Introduction to Asynchronous Sample Rate Converters (ASRC) for Jitter Reduction*
Jitter on the clock that drives the DAC will increase noise and distortion. The effect is more significant as the incoming audio signal to the DAC increases in frequency.
An Asynchronous Sample Rate Converter (ASRC) is built into all ESS DACs. Looking at the chart in Part I, it can be seen that separate ASRC ICs, placed before the DAC, were deployed in a few products. ASRCs may also be imbedded in the DSP chips in which case it is impossible to identify from the schematics. Since the ASRC is directly before the DAC, it will attenuate jitter of digital sources such as SPDIF, HDMI and asynchronous USB2 (older USB transceivers may generate too much jitter to be fully attenuated). If the source is encoded in lossless or lossy form it must be transcoded to linear PCM. ASRCs designs, which have been published, cannot attenuate jitter directly on a DSD (SACD) encoded signal and DSD must also be transcoded to Linear Pulse Code Modulation (LPCM) first.
ESS claims its ASRC can work directly on the DSD stream, at the DSD data rate, and will reject jitter on DSD data. I have no information on how ESS does this. Below I consider only the use of an ASRC for LPCM data.
The ASRC processes the incoming LPCM data, and the LPCM data that leaves the chip is not the same as what came in. To understand this, let us look at a conceptual ASRC. An ideal DAC is clocked with one oscillator. The DAC, after reconstruction filtering, drives an ideal ADC clocked by a different oscillator. This conceptual ASRC is illustrated as a block diagram in below.
Note that the ASRC does not produce a clock. It just provides a mechanism to interface the LPCM signal between to clocks that already exist. Clearly, the LPCM data entering the ideal DAC are not the same as what is exiting the ideal ADC if the clocks are different frequencies.
The ASRC can take in a clock with jitter on the LPCM input side and produce a jitter-free clock on the LPCM output side. Does this not imply all the jitter has been rejected? No! The effects of the jitter (increased SNR and distortion above what is measured with jitter-free clocks) may be present on the LPCM data exiting the ASRC. The worst-case situation is the mixed-signal example shown above. The DAC rejects none of the jitter on the clock driving it. All the distortion and noise resulting from the jitter is now part of the LPCM data leaving the ADC.
ASRCs, in practice, are fully digital and have no internal DAC or ADCs. A fully digital ASRC interpolates (up-samples) the LPCM input data to a very high sampling rate, which is then re-sampled at the output clock's rate. The system just described is impractical to integrate. Digital designers have developed systems that can emulate the functionality in less silicon.
Artefacts from the design limitations for a practical all-digital ASRC are small frequency response variations and distortion components in the LPCM data at the output. These arise in the process of the sample-rate conversion (no jitter on the clocks).
A practical fully-digital chip ASRC will reject some jitter. A section of the digital circuitry estimates the frequency ratio of the two clocks. The rate at which this estimate can change is limited. Robert Adams, who created the first ASRC for an audio application, points out the estimate is "computed using thousands of past input and output sample clock events and is therefore immune to small perturbations in the arrival time of any clock edge."
The ratio estimate becomes less effective the faster the clock edge arrival time changes. Some ASRC data sheets offer a graph that demonstrates how fast the clock edge arrival times must vary for the ratio estimator to become insensitive to it. While this graph is useful for the designer of the Pre/Pro, it cannot replace graphs showing SNR and distortion increase with different types of jitter present on one of the clocks.
*See Note following Conclusions
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