Technical & Editorial

AVR - Audio Video Receiver - Build Quality: Part II - Design of High-Performance AVRs and Pre/Pros


Quasi Current-Mode Interface for ESS DACs with a Single Operational Amplifier

An ESS DAC achieves its best THD performance when directly connected to a current-to-voltage conversion circuit (I/V) made with an op-amp section. The ESS DAC, which has balanced outputs, requires two op-amps for its current-to-voltage function. A third op-amp supports the balanced-to-single-ended converter. An identical three op-amp topology is required for DACs which have current outputs for each channel discussed above.

Traditional current-mode DACs embedded within an AVR cost at least $1,800 (refer to the chart in Part I). The combined cost of the high-performance DACs and two op-amps per channel cannot be absorbed in lower-priced AVR.

If the output pin of a current-mode DAC is shorted, its output current will flow through the short. Alternatively, when the output pin is an open circuit, the output, uselessly, moves to a power rail. The current-to-voltage converter represents a short circuit to the current-mode DAC. As the name implies, the output voltage is proportional to the DAC current.

A voltage-mode DAC has a small output impedance. In turn, the value of the voltage at the output pin is unaffected by a load provided above about 2 kOhm. The balanced-to-single-ended converter typically has a higher input impedance. Only one op-amp is needed to perform the balanced-to-single-ended operation. As discussed above, the best voltage-mode DACs have higher distortion than most current-mode DACs.

The ESS DACs use a different output stage topology. One way to model the output pin as a current source is to have it in series with a resistor with an approximate value of 780 ohms. If the output pin is shorted, the current flows through the current source into the short, and no current flows in the resistor. When the output pin is open, a voltage will appear. The voltage is found by Ohm's Law. If the current source has a value of 1 mA, then a value of 780 mV is at the output. The value of the resistor on the integrated circuit varies slightly with the voltage across it. This is the resistor's voltage coefficient which was discussed in the volume control section above. This change adds undesired distortion.

To reduce the distortion, ESS engineers have devised a novel single op-amp balanced-to-single-ended converter for the DAC. The design takes advantage of the internal resistor in the ESS DAC, using it as part of the converter. With this special circuitry, the voltage variation at the ESS output pin is reduced by ¼ compared to an open circuit. Less swing implies lower distortion.

ESS DAC distortion rises above that reported in the chart in Part I when the DAC is connected to a single op-amp circuit. The best performance requires three op-amps. AVR and Pre/Pro designers that want to replace a voltage-mode DAC with an ESS DAC of equivalent cost may use the single op-amp solution to maintain a constant external cost count. The high SNR of the ESS DAC and its ability to reject jitter are unchanged. The chart in part I identifies AVRs that use the Quasi Current-Mode Interface with an ESS DAC with note #3.

Yamaha uses this circuit in all of the current products with ESS DACs, including the top of the line CX-A5000 review soon to be published in Secrets. In the time domain, a 24 bit sine wave -90 dB below full scale shows low noise around the waveform. The distortion performance of the CX-A5000 is disappointing, although measuring at the output does not allow identification of the source as the circuit above or the single chip LSI AVR that follows in the CX-A5000.

Part III of this article series will be: An Introduction to Asynchronous Sample Rate Converters (ASRC) for Jitter Reduction and Introduction to Digital Filtering of an LPCM Signal and DAC digital filter performance. Some of this material is also covered in my review of the HK 990.

There will also be new material that includes building a Pre/Pro with pre-designed boards and methods to perform low distortion switching with SSI CMOS IC blocks. In addition, there will be a more detailed view of the internal signal flow in the LSI analog AVR chip, identifying the sources of sub-standard noise and distortion performance.